High speed serial communication is an important function in many communication systems. A continuous time linear equalizer (CTLE) is a necessary circuit in a receiver system for high speed serial link communications. A CTLE performs equalization in an analog domain by properly shaping high frequency content with respect to the low frequency content of the received signal. This analog domain equalization helps in any necessary subsequent equalization and detection either in the analog domain or the digital domain. A CTLE needs to be adapted to give proper high frequency shaping for various operating conditions.
Normally, a CTLE has two stages including one stage that targets the middle band frequency shaping and another stage that targets the frequency around the Nyquist frequency. Many CTLE circuits are implemented with a decision feedback equalizer (DFE) circuit. Conventional CTLE adaptation circuits control the high frequency shaping by either examining the zero crossing signatures of the signal (in non-DFE mode) or the tail of DFE taps (in DFE mode), which are used after the CTLE stages to cancel out the post-cursor ISI. That is, the tail of DFE taps represents an indication of the mid-band frequency content of the signal after CTLE stages.
However, conventional CTLE implementations have considerable drawbacks. For example, the zero crossing information needs oversampling clocks that consume power at high data rate. Also, DFE equalization either in the analog domain or the digital domain requires considerable power to achieve the desired high data rate. Finally, a CTLE adaptation based on DFE taps in the time domain is associated with a DFE adaptation, which may result in interactions between the CTLE adaptation and the DFE adaptation, causing an unstable receiver or compromised bit error rate (BER) performance.
Accordingly, circuits and methods which enable the adaptation of an equalizer circuit while overcoming the drawbacks of conventional circuits are desirable.